1. Field of the Invention
The present invention relates to a semiconductor device and a technique of storing information in a nonvolatile memory unit that is provided in a semiconductor device for controlling the semiconductor device. For example, the present invention relates to a semiconductor device including both a memory cell that stores therein data in a reversible manner and a memory cell that stores therein data in an irreversible manner, such as a semiconductor memory including a defective address memory circuit. Furthermore, the present invention relates to a writing method for storing information in a nonvolatile memory unit that is provided for controlling an internal operation of the semiconductor device.
2. Description of Related Art
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a defective address is saved by replacing a defective cell that does not perform a normal operation with a redundant cell. Generally, a fuse element is used for storing the defective address. The fuse element in an initial state is in an electrically conductive state. By blowing the fuse element with an application of a laser beam, it is possible to store the defective address in the fuse element in a nonvolatile manner. Therefore, arranging a plurality of such fuse elements and blowing desired ones from among the fuse elements makes it possible to store desired addresses. In this manner, a general fuse element stores therein information in a nonvolatile manner by changing its state from a conductive state to an insulating state.
On the other hand, an antifuse element has been attracting attention in recent years. Unlike the general fuse element, the antifuse element stores therein information by changing its state from an insulating state to a conductive state. Writing of data in the antifuse element is performed by an insulation breakdown by an application of a high voltage. Therefore, unlike the general fuse element, the antifuse element does not require an irradiation with a laser beam to write information. As a result, it is possible to perform writing of a defective address at high speed, and at the same time, a dedicated apparatus such as a laser trimmer is not necessary. In addition, because it does not cause any damage to a passivation layer and the like due to an irradiation with a laser beam, it is also possible to enhance the reliability of a product.
The writing of the defective address in the antifuse element is performed after an operation test of devices in the wafer state. The operation test in the wafer state is not performed on a chip-by-chip basis, but is generally performed for a plurality of chips in a parallel manner. By connecting clock terminals, address terminals, and command terminals in common to a plurality of chips to be tested, a clock signal, an address signal, and a command signal are supplied in common to the chips, and in this state, read or write operation is actually performed. As for input/output data, at least, it needs to be input or output independently for each of the chips, data input/output terminals of the chips are not connected in common, which is matter of course.
In this way, at the time of the operation test in the wafer state, because the address terminals are connected in common to a plurality of chips to be tested, it is not possible to supply an independent address to each of the chips. However, a defective address that is supposed to be detected is naturally different for each of the chips. Therefore, the writing of the defective address needs to be performed for each of the chips, and it is impossible to write the defective address in a plurality of chips in parallel. That is, although the operation tests of a plurality of chips can be performed in parallel, the writing of the defective address needs to be performed independently for each of the chips.
The writing of the defective address in the antifuse element can be performed at high speed as compared to the case that the defective address is written in a fuse element by an irradiation with a laser beam. However, because the writing of the defective address in the antifuse element is performed by an application of the high voltage, it takes a considerably long time as compared to normal input and output of data. For example, if there are 1000 fuse sets each of which can store one address, and if the write time for a single fuse set is 5 milliseconds, it takes about 5 seconds per chip to perform writing of data for all the fuse sets.
As a method to cope with such a problem, a method has been proposed in which a dedicated latch circuit for temporarily storing a defective address is provided, and after the defective address being written in the latch circuit, the writing process in the antifuse element is actually performed (see Japanese Patent Application Laid-open No. 2004-303354). Because the writing process in the latch circuit can be performed in a remarkably short time, it is possible to complete a supply of the defective address to each of the chips in a short time. The actual writing processes in the antifuse elements are then performed for a plurality of chips in parallel, which makes it possible to perform the writing process in the antifuse element at high speed.
However, the dedicated latch circuit for temporarily storing the defective address and the like causes an increase of the chip dimension. Furthermore, the latch circuit is only used for writing the defective address and is no longer used thereafter. Therefore, the increase of the chip dimension due to such a circuit is not desirable.
The above problem is not limited to the case that a defective address is written in an antifuse element, but occurs also in other cases in a semiconductor device that includes both a memory cell for storing data in a reversible manner and another memory cell for storing data in a nonvolatile manner in which desired information (such as a program) is written in the another memory cell.
The present inventors have carried out an examination of a semiconductor device that can write desired information in a memory cell for storing data in a nonvolatile manner at high speed while preventing an increase of the chip dimension, based on recognition of the above problems.